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MC3423
1
+
30
Power
Supply
6
R2 = 2.7 k
Max
Typ
#1
7
R1
10k
?
20
10
Min
1
+
Power
Supply
#2
7
5
Q1
1.0k
?
0
0
5.0 10 15 20 25
V T , TRIP VOLTAGE (V)
Figure 9. R1 versus Trip Voltage
30
Figure 8. Circuit Configuration for
Activating One MC3423 from Another
35
Note that both supplies have their negative output
leads tied together (i.e., both are positive supplies). If
their positive leads are common (two negative supplies)
the emitter of Q1 would be moved to the positive lead of
supply 1 and R1 would therefore have to be resized to
deliver the appropriate drive to Q1.
Crowbar SCR Considerations
Referring to Figure 11, it can be seen that the crowbar
30
25
20
15
R G(min) = 0
if V CC < 11 V
SCR, when activated, is subject to a large current surge
from the output capacitance, C out . This capacitance
10
0
10 20 30 40 50 60 70
80
consists of the power supply output caps, the load’s
decoupling caps, and in the case of Figure 11A, the supply’s
input filter caps. This surge current is illustrated in Figure
12, and can cause SCR failure or degradation by any one
of three mechanisms: di/dt, absolute peak surge, or I 2 t. The
RG, GATE CURRENT LIMITING RESISTOR ( W )
Figure 10. Minimum R G versus Supply Voltage
interrelationship of these failure methods and the breadth
of the applications make specification of the SCR by the
1.0
1
2 3 5 7 1
semiconductor manufacturer difficult and expensive.
Therefore, the designer must empirically determine the
SCR and circuit elements which result in reliable and
effective OVP operation. However, an understanding of the
factors which influence the SCR’s di/dt and surge
capabilities simplifies this task.
0.1
0.01
di/dt
As the gate region of the SCR is driven on, its area of
conduction takes a finite amount of time to grow, starting
0.001
0.0001
1
5
2
1
as a very small region and gradually spreading. Since the
0.001
0.01
0.1
1.0
10
anode current flows through this turned?on gate region,
very high current densities can occur in the gate region if
high anode currents appear quickly (di/dt). This can result
in immediate destruction of the SCR or gradual
degradation of its forward blocking voltage capabilities ?
depending on the severity of the occasion.
http://onsemi.com
5
t d , DELAY TIME (ms)
Figure 11. Capacitance versus
Minimum Overvoltage Duration
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